A/D documentation

The A/D will be discussed at the top level first and then the smaller blocks will be discussed in greater detail. The A/D was simulated using a Mixed Signal methodology using Cadence tools since 10,642 transistors takes over 2 days to simulate using an all transistor model. Also included here is a spec for the A/D.

This is the top level view: Since nothing can be seen from this I have included a .pdf version. Underneath is an image of how the Comparators are hooked up to the resistor string, and how the NAND2's with the inverting inputs convert the string of 0's and 1's output by the comparator into a single bit code. For example if the input voltage is half of the reference, then the bottom half of the comparators would output a zero and the top half would output ones. This is then converted into a 255-bit bus which is now a string of 1's except for one lone zero where the transition occurs, the location of this zero is then encoded into an 8-bit binary number by the ENC256 block. It's operation is described in the "Larger Digital Blocks" section.

Blown up below is the rest of the circuitry, this schematic includes some "test equipement." This includes an ahdl model of a sample-and-hold and a DAC to test the output of the A/D. The circuit behaves in the same way as described by the specification document at the top of the page.



Comparator

# of Cells Used# of TransistorsTotal
255307650

Larger Digital Blocks

NameDescriptionDaugther CellsQty# of Tran.# of Instances
256 to 8 EncoderConverts the outputs of the NAND's to an 8-bit binary valueENC16
OR16_4
17
1
17181
16 to 4 EncoderChecks a 16-bit bus for a 1 to 0 transitionNAND4
INV
OR2
NOR4
AND2
6
3
3
2
1
9417
LSB ORORs the LSB outputs from the 16 ENC16 blocksOR4201201
Output RegistersDescriptionDaugther CellsQty# of Tran.1


Standard Cells:

NOR4
INV
NameDescriptionDaugther CellsQty# of Tran.# of Instances
AND2Min. Dimension 2-input ANDNAND2
INV
2
2
617
BUFMin. Dimension BufferINV24???
BUFx3Buffer with 3x outputINV
INVx3
1
1
8???
DFFMin. Dimension D flip-flopINV
TG
5
4
188
INVMin. Dimension Inverternone-291
INVx3Inverter 3x outputnone-6???
NAND2Min. Dimension 2-input NANDnone-4???
NAND2_1INVMin. Dimension 2-input NAND with inverted B inputNAND2
INV
1
1
6???
NAND4Min. Dimension 4-input NANDnone-8???
NOR2Min. Dimension 2-input NORnone-4???
NOR4Min. Dimension 4input NORnone-8???
OR2Min. Dimension 2-input ORNOR2
INV
1
1
6???
OR4Min. Dimension 4-input ORnone1
1
10???
TGMin. Dimension Transmission gatenone-2???
NOTE: the notation for the testing of propagation delays is as follows:
L indicates a low logic level
H indicates a high logic level
R indicates a rising edge
F indicates a falling edge
What I tried to do was to measure the propagation delay with every combination of inputs that caused a change at the output. Then I took the slowest cases and put those numbers into the verilog models. Also slightly pesimistic was the load of a NAND4 at the output of the cell being tested, but this helps account to interconnect parasitics.


Total transistor count: 10,642

Final thoughts: Plans for the Future


Questions? Comments? Email me: iknausz@lsil.com