My Second Patent - #7,504,979 - An Low Power DAC


System and method for providing an ultra low power scalable digital-to-analog converter (DAC) architecture

USPTO Link  read more »

My First Patent - #7,362,173 - CMOS Amplifiers


System and Method for Providing Slew Rate Enhancement for Two Stage CMOS Amplifiers

Google Patent Link  read more »

2006 International Solid State Circuits Conference, San Francisco, CA


A 250µW 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers

I presented this paper at the 2006 ISSCC, it can be found on IEEE eXplore, it is a copyrighted document. The architecture and design methods are presented for implementing N-bit DACs optimized for small-format LCD column drivers. Individual 9b DACs in a 12-channel QVGA display system occupy a die area of 0.042mm2. This represents a composite DAC performance of better than 0.60pJ/b/mm2. (Published paper available upon request)

An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications


This thesis will examine and develop electronic circuits for driving small format LCD technology commonly found in portable devices. Display technologies of at least ¼ VGA resolution (320 x 240 pixels) are considered. Several technologies are being employed to create displays of this resolution. This thesis will examine and develop a display driver for the latest generation of LCD technology currently in production.

Please see the paper attached below.

A Methodology and Laboratory Setup for Digital to Analog Converter Testing


This paper will discuss a methodology for testing Digital to Analog (DAC) converters. An efficient
Lab Setup with a high level of reuse will be described. Also discussed will be implementation details of
various tests.  read more »

Grounded Gate ESD Protection - Modeling and Characterization


The purpose of this paper is to review the Grounded Gate Electrostatic Discharge (ESD) protection scheme, model the two NMOS device breakdowns, evaluate use of the models for design and finally to explore some of issues involved with the use of Grounded Gate NMOS devices as protection devices in modern deep submicron processes. Grounded Gate protection structures are very commonly used to protect integrated circuits during ESD events because of their relative ease of implementation and compactness.  read more »

“Pong” the Game


A simple synthesizable VHDL Pong game. Uses PS/2 keyboard and has VGA output. Implemented on an Altera Flex FPGA board. Please see the paper attached below.

White paper on LCD technologies


A White paper on LCD technologies, please see attached below.

A 6-bit Fully Segmented Current Mode DAC in RIT 2μm Process


This paper describes a high relatively high performance DAC designed in the RIT 2um process. The DAC is a traditional fully segmented architecture. It has 6 bits of resolution and operates at up to 20MHz at an operating voltage of 5V. Please find the paper attached below.

A 2.4GHz Low Noise Amplifier (LNA)


This paper describes a LNA designed in the IBM 0.25um RF CMOS process. The LNA has a single tuned frequency of 2.4GHz. The LNA is a simple class A amplifier. Please find the full paper attached below.

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