My Second Patent - #7,504,979 - An Low Power DAC

in

System and method for providing an ultra low power scalable digital-to-analog converter (DAC) architecture

USPTO Link

A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.

project

respected sir iam doing the masters degree project on the above mentioned ieee paper so can i get th detailed information on that paper .

DAC Project

Hi Rajesh, I will do my best to answer any specific question that you have. Please go ahead and ask and I will help. Regards, Imre

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